In state of the art process technologies such as those with line widths of 65 nanometers (nm) and 90 nanometers, there is significant sub-threshold leakage in cells even if the cell is in a steady state. Ideally in Static Random Access Memory (SRAM) memory circuits if a cell is not switching, no current should be drawn. However, as line widths get smaller, leakage becomes a problem even when the cells are not switching i.e., when the cells are in standby mode. This is a concern in battery powered and mobile applications where power conservation is of great importance. Furthermore SRAM circuits need to be able to wake from standby mode (where very little/no current is drawn) to active mode (where circuit is operating normally) very quickly.
A number of conventional chip leakage solutions for reducing the chip leakage power are described. In a first conventional solution the chip power supply is reduced during standby conditions and brought back to nominal voltages during active mode. Disadvantages of this first conventional solution include that the chip power supply needs to be brought back higher during active condition which means there is a startup time from standby to active. Also, this first conventional solution needs to be implemented as a die-by-die tweak because it is not a closed loop system.
In a second conventional solution low speed, high threshold voltage (Vt) or multiple Vt technologies are used to lower current leakage. Employing a high Vt technology slows down the entire chip, because the high threshold voltage causes all transistors to switch slowly. Solutions employing multi-Vt technologies are expensive due to the additional mask steps required to implement multi-Vt technologies during wafer manufacturing. For example, using older high line-width technologies such as 0.25 micrometer (um) or 250 nanometer (nm) technologies, a full mask set cost approximately one hundred thousand US dollars. Today a full mask set using cutting edge 65 nm technology costs approximately nine hundred thousand US dollars, with a cost of fifty thousand US dollars for each additional mask step. With such expensive technologies, using additional masks to implement multi-Vt technologies is a pricey solution. Furthermore, with multi-Vt technologies there is no feedback mechanism based on transistor leakage to control leakage current with process, voltage and temperature (PVT).
In a third conventional solution a constant substrate reverse bias reference voltage is set at wafer sort by doing a die by die tweak to get to the optimal substrate bias voltage for each die. This reverse bias operation uses a negative reference voltage for N-channel transistors, and uses a positive reference voltage for P-channel transistors. This die-by-die tweak costs additional test time per die, and the bias does not change automatically with voltage and temperate i.e. this is an open loop system with no feedback.
In a fourth conventional solution shown in FIG. 1 a speed to voltage converter circuit 100 may be used to control power supply. The speed to voltage converter 100 comprises an input signal 110, which may be a clock or other periodic signal, coupled to a replica delay path block 130 which introduces a propagation delay time (Tpd). The output of the replica delay path block 130 is coupled to an input of a speed to voltage converter block 140, which generates a voltage proportional to the propagation delay time. The output of the speed to voltage converter block 140 is coupled to a first input of a comparator 150. A reference voltage block 120 provides a bandgap reference to a second input of the comparator 150. The output of the comparator 150 is coupled to a voltage and bias generator block 160. The output of this bias generator block 160 is used to bias the transistors in the device. The speed (or frequency) to voltage converter can also be used to regulate speed by comparing the speed of a replica circuit with a reference voltage such as that produced by a bandgap.
Disadvantages of the fourth conventional solution include that since this solution changes the power supply voltage or bias based on the speed of a circuit (the delay of a delay chain), this is not a direct and accurate representation of the leakage in a device. Hence the leakage reduction is not optimal. Furthermore, delay circuits are usually slower at high temperatures making the feedback system operate as if it is a slow corner or a less leaky corner and hence the substrate bias is not applied. But the sub-threshold leakages are indeed worse at higher temperatures and hence the substrate bias should be applied. This difference in temperature dependence of delays and sub-threshold leakage make this feedback scheme unsuitable for reducing leakage power.
In a fifth solution, the leakage is reduced to a minimum possible level by finding a bias point based on the combination of GIDL (gate induced drain leakage), sub-threshold current and gate leakage currents. But this effectively reduces the speed of the circuit during active mode because the minimum leakage point corresponds to a slow corner which is slow in terms of speed. Hence, to get better speed during active mode, the reverse substrate bias has to be removed or reduced during active mode which takes time (typically in the high hundred of nanoseconds or low microseconds). This increases standby to active access time which is a very critical specification for memory circuits (for example, the standby to active time of memory circuits are in the single digit nanoseconds).
It would be desirable to have solution that reduces the chip leakage power based on a low ripple/noise feedback scheme that is derived from leakage parameters of a device and also works across process, voltage and temperature. It is also desirable that the same substrate bias be used during standby and active mode to not affect standby to active access time in high speed memories. Since memory chips are usually designed to meet speed, leakage and active power optimally at the typical corner for highest yield, the goal of the ideal feedback solution is to make fast/leaky process corners and high voltage/temperature corners look like a typical PVT corner (which has lower leakage power without sacrificing speed specifications).